1. Field of the Invention
The present invention relates to electroplating, and more particularly, to an electrolyte for use in plating copper to form interconnects of a semiconductor device, and an electroplating method using the same.
2. Description of the Related Art
As semiconductor devices become more highly integrated, the use of copper in forming interconnects of semiconductor devices is increasing due to its low resistance. When copper is used to form interconnects, a conventional metal interconnect forming process including deposition and etching of the metal layer cannot be applied, because copper is incapable of dry etching. Thus, a damascene process is applied to form copper interconnects: via holes or trenches corresponding to a desired interconnect pattern are formed in a substrate and are filled with copper by electroplating, and then the copper layer is etched by chemical mechanical polishing (CMP).
As described above, the electroplating process is necessary to form the copper interconnect. However, a problem occurs in filling the via hole or trench by electroplating. As pattern size becomes smaller with the increase in the integration density of semiconductor devices, the aspect ratio of the via hole to be filled increases. As a result, uniform filling of the via hole becomes difficult. For example, the entrance of a via hole having a relatively high current density is first filled, rather than the inside of the via hole, thereby resulting in voids within the via hole. As a result, the resistance of the interconnect increases. To overcome these problems, a polymer capable of suppressing adsorption of copper on the wide flat surface of interconnect patterns, and capable of filling the via hole or trench by facilitating the growth of the plated layer from the bottom of the via hole or trench, is added. However, as the pattern size becomes smaller and the aspect ratio becomes larger, it becomes difficult to use a polymer additive to improve the filling characteristic.
Meanwhile, the flatness of the surface of a copper layer formed by electroplating affects the following CMP process. Since the section of the substrate which has undergone an etching process to form interconnect patterns has grooves (via holes or trenches) and projections, a copper layer deposited on the substrate by electroplating has steps. With regard to planarizing the surface of the copper layer to eliminate the steps, which is referred to as xe2x80x9clevelingxe2x80x9d, many approaches have been taken to improve the flatness of the copper layer by addition of a brightener, a leveler and/or a wetting agent, as shown, for example, in U.S. Pat. Nos. 4,134,803 and 5,849,171. U.S. Pat. No. 4,134,803 discloses a copper-plating electrolyte containing a disulfide having the formula of [RRNNCS2]2, and a halo hydroxy sulfonic acid having the formula of X(CH2)nCHOH-CH2SO3M. Meanwhile, U.S. Pat. No. 5,849,171 discloses a copper-plating electrolyte containing a naphthol compound such as a xcex2-naphtholalkoxylate, as a wetting agent, and a phenazonium compound.
Besides the additives disclosed in the above-mentioned references, a variety of polymer additives have been suggested to improve the flatness of the copper layer. However, since the above-mentioned references are limited to filling just a through hole of a printed circuit board (PCB) or to improving the glossiness of plating for aesthetic purpose, the conventional electrolytes cannot be applied in forming a highly integrated semiconductor device having a fine pattern less than 1 xcexcm. As an example of the limitation, the copper layer deposited on a region having a relatively high pattern density swells up so that the region becomes thicker than other regions. This phenomenon is referred to as overplating. The margin of thickness removed by CMP is so small that the substrate with the overplated copper layer cannot be polished into a uniform surface, which acts as a defective factor.
In general, both smaller patterns having a critical dimension (CD) less than 1 xcexcm and a high aspect ratio, and larger patterns having a CD larger than 1 xcexcm and a low aspect ratio exist on the semiconductor substrate. As previously described, overplating, i.e., excessive growing of plated layer, occurs on the region having a relatively high pattern density with a CD less than 1 xcexcm. On the other hand, the thickness of the plated layer on the region having a relatively large CD becomes thin. The poor flatness of the plated layer makes application of the subsequent CMP process difficult.
As described above, in order for electroplating with copper to be applied in manufacturing semiconductor devices, there is a need for an electroplating technique capable of filling a fine pattern less than 1 xcexcm, and capable of uniformly plating copper over the fine pattern to ensure a successful CMP process after the plating process.
A feature of the present invention is to provide a copper-plating electrolyte, and a method for forming a copper interconnect of a semiconductor device by electroplating using the electrolyte, in which a via hole or trench having a critical dimension (CD) less than 0.3 xcexcm and an aspect ratio greater than 4, which is formed in a semiconductor device having a fine pattern less than 1 xcexcm, particularly, a CD of 0.13 xcexcm, can be smoothly filled with the electrolyte, resulting in the copper interconnect having excellent surface flatness.
According to an aspect of the present invention, there is provided a copper-plating electrolyte. The copper-plating electrolyte includes an aqueous copper salt solution, a water-soluble xcex2-naphtholethoxylate compound having the formula 
where n is an integer from 10 to 24, a disulfide having the formula XO3S(CH2)3SS(CH2)3SOX3 or a water-soluble mercaptopropanesulfonic acid or salt thereof having the formula HS(CH2)3SO3X, where X is sodium, potassium, or hydrogen, a water-soluble polyethylene glycol having a molecular weight ranging from about 4,600 to about 10,000, and a water-soluble polyvinylpyrrolidone having a molecular weight ranging from about 10,000 to about 1,300,000.
According to another aspect of the present invention, there is provided an electroplating method for forming a copper interconnect of a semiconductor device. The electroplating method includes the steps of forming a predetermined pattern containing a trench or via hole, preferably having a critical dimension (CD) less than 1 xcexcm and an aspect ratio larger than 4, on a semiconductor substrate, and electroplating the semiconductor substrate having the predetermined pattern with a copper-plating electrolyte as described herein.
In particular embodiments, the aqueous copper salt solution contains chlorine ions.
In more specific embodiments, the amount of the disulfide or the mercaptopropanesulfonic acid or salt thereof is in the range from about 0.001 to a bout 0.05 g per liter, the amount of the polyethylene glycol is in the range from about 0.001 to about 10 g per liter, the amount of the xcex2-naphtholethoxylate is in the range from about 0.05 to about 3.0 g per liter, and the amount of the polyvinylpyrrolidone is in the range from about 0.001 to about 0.2 g per liter.
Semiconductor devices produced according to the inventive method are also provided.
According to the present invention, a via hole or trench having a CD less than 0.3 xcexcm and an aspect ratio greater than 4 can be fully filled with the electrolyte without causing voids therein. In addition, no overplating occurs in regions including a relatively large number of such small via holes or trenches.